1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and, more particularly, to a metal oxide nitride oxide semiconductor (MONOS) type of nonvolatile semiconductor storage device.
2. Description of the Prior Art
There are two major types of nonvolatile storage elements formed as MIS transistors: those using the metal nitride oxide semiconductor (MNOS) type transistor, and those using the floating gate (FG) type transistor.
In the MNOS type element, information charge is accumulated in an interfacial region or the like formed in a boundary region in a two-layer insulating film. Elements of this type include those called MONOS having a silicon oxide film on a silicon nitride film, and also include those having various combinations of insulating films other than this combination of silicon oxide film and silicon nitride film.
The FG type element has a two-layer gate electrode structure in which information charge is accumulated on a floating gate electrode, which is a first gate electrode. In this structure, the first gate electrode is formed in a floating state on a silicon oxide film on a major surface of a semiconductor substrate, an interlayer insulating film in which a silicon oxide film and a silicon nitride film are combined is provided on the first gate electrode, and a second gate electrode, which is a control gate electrode, is formed on the interlayer insulating film. The first gate electrode is covered with the second gate electrode.
Basically, nonvolatile memories called xe2x80x9cflash memoryxe2x80x9d can use the above-mentioned M(O)NOS transistor or the FG transistor as their nonvolatile storage element. In all the current mass-produced flash memories, however, only FG transistors are used as a nonvolatile storage element. However, the information charge holding characteristic of FG transistors theoretically recognized is not satisfactorily high, and there is a need to use a silicon oxide film having a comparatively large thickness of 9 nm or more as a tunnel oxide film between the semiconductor substrate major surface and the floating gate electrode. Therefore there is a limit to the reduction in the voltage for write/erase of information charge.
On the other hand, in MNOS transistors, the film thickness of the tunnel oxide film between the semiconductor substrate major surface and the silicon nitride film can easily be reduced, and a thin silicon oxide film of 3 nm or less can be used. Therefore, it is theoretically possible to reduce the operating voltage, particularly the voltage for write/erase of information charge. Operations for writing and erasing information charge in this type of nonvolatile storage element are as described below. That is, in MNOS transistors, information charge is written by injecting electrons from the semiconductor substrate into the above-mentioned interfacial region through a direct tunnel in a silicon oxide film about 2 nm thick formed on the semiconductor substrate major surface, and information charge is erased by a reverse operation, i.e., releasing electrons from the interfacial region to the semiconductor substrate. Such an interfacial region is formed of as an electron capture region. The written state of information charge in such a region corresponds to stored information xe2x80x9c1xe2x80x9d, and the information charge erased state corresponds to stored information xe2x80x9c0xe2x80x9d. In recent years, various studies have been energetically made for the purpose of putting M(O)NOS transistors theoretically considered capable of reducing the write/erase voltage to practical use as a storage element in nonvolatile memories such as flash memories.
For example, U.S. Pat. No. 5,768,192 discloses the basic structure of a nonvolatile storage element, which is an instance of a MONOS transistor used as a nonvolatile storage element in a flash memory. U.S. Pat. No. 5,966,603 recently made public discloses a technique relating to a nitride read only memory (NROM) as a technique enabling a nonvolatile memory manufacturing process to be advantageously simplified (hereinafter referred to as xe2x80x9cfirst conventional artxe2x80x9d). The basic structure of the nonvolatile memory according to this art is the same as that disclosed in above described U.S. Pat. No. 5,768,192.
Further, the structure of a nonvolatile storage element proposed in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123 (hereinafter referred to as xe2x80x9csecond conventional artxe2x80x9d) is known.
The first conventional art will be described with reference to FIGS. 21 to 24. The basic operation of the above-described MONOS will also be described. FIG. 21 is a plan view of a cell array of an NROM. FIGS. 22A to 22D are cross-sectional views taken along the line Xxe2x80x94X shown in FIG. 21. FIGS. 22A to 22D show process steps for manufacturing the NROM. Description with reference to FIG. 21 will be made only of wiring in the cell array for ease of understanding.
In the cell array of the NROM, as shown in FIG. 21, a first diffusion layer 102, a second diffusion layer 103, a third diffusion layer 104, and so on are formed on a silicon substrate 101, and word lines (gate electrodes) 105, 106, and 107 are arranged perpendicularly to the diffusion layers. The diffusion layers form bit lines.
As shown in FIG. 22A, a first insulating film 108 is formed by thermal oxidation of a P-conduction type of silicon substrate 101, and a silicon nitride film is formed as a second insulating film 109 by chemical vapor deposition (CVD). After this film forming, a resist mask 110 having a diffusion layer pattern, which is a plan pattern of strips (strip pattern), is formed on the second insulating film 109 by a well-known lithography technique. The second insulating film 109 is then removed by etching. Thereafter, as shown in FIG. 22B, ions of an n-type impurity such as arsenic are implanted by using the resist mask 110 as anion implantation mask, and the resist mask 110 is removed, followed by a heat treatment. The first diffusion layer 102, the second diffusion layer 103 and the third diffusion layer 104 are thus formed in the surface of the silicon substrate 101.
Subsequently, the entire surface is subjected to thermal oxidation at a temperature of 750xc2x0 C. or higher. As shown in FIG. 22C, a non-diffusion-layer insulating film 111 having a thickness of 100 nm is formed by this thermal oxidation on the surfaces of the first diffusion layer 102, the second diffusion layer 103 and the third diffusion layer 104. When this thermal oxidation is performed, the surface of the second insulating film 109 is also thermally oxidized to form a silicon oxide film as a third insulating film 112. Thus, a laminated insulating film of ONO structure constituted by the third insulating film 112 (silicon oxide film), the second insulating film 109 (silicon nitride film) and the first insulating film 108 (silicon oxide film) is formed.
Subsequently, a tungsten polycide film having a film thickness of about 200 nm is deposited as an electroconductive film on the entire surface and is processed by well-known lithography and dry etching techniques to form the word line 105.
Thus, as shown in FIG. 22D, bit lines for NROM cells are formed on the silicon substrate 101 by the first diffusion layer 102, the second diffusion layer 103, the third diffusion layer 104, and so on; information charge write/erase regions are formed by the first insulating film 108, the second insulating film 109 and the third insulating film 112 formed in the ONO structure; and the word lines 105, 106, and 107, also shown in FIG. 21, are arranged. A basic NROM cell structure is thus formed.
The basic operation of the MONOS transistor having the above-described NROM cell basic structure will be described. An operation for writing information charge (electrons in this case) is as described below. As shown in FIG. 23A, the silicon substrate 101 and the first diffusion layer 102, for example, are fixed at ground potential, VW of the second diffusion layer 103 is set to 1 to 2 V, and VGW of the gate electrode 105 is set to about 5 V. That is, the voltage settings are such that the MIS transistor operation of the MONOS transistor is in a linear characteristic condition. When these voltages are applied, an electron current 113 (channel current) is caused to flow from the first diffusion layer 102 functioning as the source to the second diffusion layer 103 functioning as the drain to generate channel hot electrons (CHE) in the vicinity of the second diffusion layer 103. Part of the channel hot electrons pass through the barrier formed by the first insulating film 108 to be captured in a region in the second insulating film 109. This region is shown as a capture region 114 in FIG. 12. Thus, in writing electrons, information charge is accumulated in a region in the second insulating film 109 near the end of the second diffusion layer 103.
An operation for reading information in the above-described MONOS transistor is as described below. As shown in FIG. 23B, voltage settings are made conversely to those described above, that is, the second diffusion layer 103 functioning as the source is fixed at ground potential, VR of the first diffusion layer 102 functioning as the drain is set to 1.5 V, and VGR of the gate electrode 105 is set to about 3 V. Also in this case the silicon substrate 101 has ground potential.
When read-out is performed in this manner in the case where the information as a result of write of electrons in the capture region 114 is xe2x80x9c1xe2x80x9d, no current flows between the first diffusion layer 102 and the second diffusion layer 103. In contrast, in the case of information xe2x80x9c0xe2x80x9d, i.e., in the case where no electrons are written in the capture region 114, a current flows between the first diffusion layer 102 and the second diffusion layer 103. Written information can be read in this manner.
An operation for erasing information in the above-described MONOS transistor is as described below. In the structure shown in FIG. 23A, the silicon substrate 101 and the first diffusion layer 102, for example, are fixed at ground potential, VE of the second diffusion layer 103 is set to 5 V, and VGE of the gate electrode 105 is set to about xe2x88x925 V. When these voltages are applied, positive holes generated by interband tunneling caused by band bending in a region at the end of the second diffusion layer 103 corresponding to an overlap on the gate electrode 105 are injected into the above described capture region 114, thus erasing the information charge.
The above-described NROM can be designed so as to have a two-bit/one-cell configuration, as described below with reference to FIG. 24. As shown in FIG. 24, NROM cell bit lines are formed by a first diffusion layer 102, a second diffusion layer 103, etc., on a silicon substrate 101 and covered with an on-diffusion-layer insulating film 111, and information charge write/erase regions are formed by a first insulating film 108, a second insulating film 109 and a third insulating film 112 in an ONO structure. In the NROM, information charge write regions formed in two places, i.e., a first-bit capture region 114 and a second-bit capture region 115 formed as electron capture regions, are used. The operation in this case is basically the same as that described above with reference to FIGS. 23A and 23B. Thus, a multibit design can be made and NROM cells of the above-described two-bit/one-cell configuration can be provided.
The second conventional art will be described with reference to FIG. 25. FIG. 25 is a cross-sectional view of a cell array of a nonvolatile memory. This nonvolatile memory is characterized by forming word lines and control gate wiring in a memory cell array structure.
As shown in FIG. 25, a first diffusion layer 202, a second diffusion layer 203 and a third diffusion layer 204, which are N+ diffusion layers, for example, are formed in a major surface of a silicon substrate 201 of a P-conduction type. First control gate electrodes 205, second control gate electrodes 206 and gate electrodes 207 are formed on the silicon substrate 201 generally in correspondence with the place between the first diffusion layer 202 and the second diffusion layer 203 and the place between the second diffusion layer 202 and the third diffusion layer 204, with an insulating film interposed between each gate electrode and the silicon substrate 201. In each memory cell, the first control gate electrode 205 and the second control gate electrode 206 are provided as the above-mentioned control gate wiring. The insulating film between each control gate electrode, i.e., the first (second) control gate electrode 205 or 206, and the silicon substrate 201 is an insulating film of an ONO structure similar to that in the first conventional art, i.e., a multilayer insulating film of an ONO structure formed of a first insulating film 208 (silicon oxide film), a second insulating film 209 (silicon nitride film) and a third insulating film 210 (silicon oxide film). The insulating film between each gate electrode 207 and the silicon substrate 201 is a single-layer silicon oxide film, which is formed of the first insulating film 208 (silicon oxide film), for example. The first (second) control gate electrode 205 or 206 and the gate electrodes 207 are also separated electrically from each other by the above-described insulating film in the ONO structure.
As shown in FIG. 25, an interlayer insulating film 211 is formed and a word line 212 is provided in a state of being connected to the above-described gate electrodes 207.
In the thus-constructed memory, information charge (electrons) is written to a capture region in the ONO structure below the first (second) control gate electrode 205 or 206 described above. When an operation for erasing information charge is performed, a voltage is applied between the first (second) control electrode 205 or 206 and the first (second) diffusion layer 202 or 203. Positive holes generated by interband tunneling such as that described with respect to the first conventional art are thereby injected into the above-described capture region.
In the nonvolatile storage element having the memory cell array of the NROM described above with respect to the first conventional art, the reduction in film thickness of the first insulating film 108, the second insulating film 109 and the third insulating film 112 is limited if a standard value of information charge accumulation holding time is ensured. The inventor of the present invention has made various trial experiments on fundamental characteristics of nonvolatile storage elements of the above-described MONOS structure, and has found that the lower limit of the thickness of insulating film of ONO structure necessary for ensuring an accumulation holding time of ten years, calculated in terms of silicon oxide film, is about 8 nm. It has also become clear that there is a limit to the increase in read-out speed in recent flash memories, which necessarily need an improvement in operating speed.
In the first conventional art, electrons written to the information charge capture region 114 drifts laterally in the second insulating film 109 formed of silicon nitride film inferior in insulating characteristic than silicon oxide film, as described above with reference to FIG. 23, so that the capture region expands with passage of time and the information charge holding characteristic becomes deteriorated. In a case where the NROM is made to operate in the two-bit/one-cell arrangement shown in FIG. 24, it is difficult to read out accumulated information if electrons written to the capture region 114 or 115 spread with passage of time. As described above, in a case where a nonvolatile storage element is made to operate in a multibit arrangement as in the case of NROM, the influence of only a slight change in electrons in the capture region with time is considerable. This is because, in the above-described case, the amount of electrons to be written is 500 to 1000 electrons and the electron capture region is considerably narrow, that is, the width from side to side is about 10 nm.
In the second conventional art, the MONOS transistor having control gate electrodes and the MOS transistor having a gate electrode are formed in one memory cell. The control gate electrodes are formed by side wall electroconductive film formed on side walls of the gate electrode. In this structure, the size of the control gate electrode in the channel direction can be reduced. Therefore, the effective channel length can be reduced to achieve an increase in the above mentioned speed of the read-out operation.
However, also in this case, the information charge capture region expends with passage of time for the same reason as that described above with respect to the first conventional art, resulting in deterioration in information charge holding characteristic.
Summary of the Invention
In view of the above-described circumstances, an object of the present invention is to provide a nonvolatile semiconductor storage device having an improved information charge holding characteristic.
A nonvolatile semiconductor storage device according to the present invention has a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate, and a first diffusion layer and a second diffusion layer formed in the surface of the semiconductor substrate on opposite sides of the gate electrode, a channel region being formed between the first and second diffusion layers, wherein a first insulating layer, isolated pieces of material and a second insulating layer are formed in order in a multilayer structure on the surface of the semiconductor substrate on the channel forming region.